{"id":29614,"date":"2021-07-21T07:57:04","date_gmt":"2021-07-21T13:57:04","guid":{"rendered":"https:\/\/goldenti.com\/site\/?p=29614"},"modified":"2021-07-21T07:57:07","modified_gmt":"2021-07-21T13:57:07","slug":"logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro","status":"publish","type":"post","link":"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/","title":{"rendered":"Logran fabricar una CPU de 4 capas, \u00bfas\u00ed ser\u00e1n los chips del futuro?"},"content":{"rendered":"\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/hardzone.es\/app\/uploads-hardzone.es\/2021\/01\/3D_Packaging-Portada.jpg\" alt=\"3DIC Intel AMD\" \/><\/figure>\n\n\n\n<p>En el primer caso podemos hablar de la V-Cache que AMD ha integrado recientemente en los CCD Chiplet de Zen 3 o la SRAM que Samsung present\u00f3 el a\u00f1o pasado. En el caso de l\u00f3gica+l\u00f3gica tenemos a los Lake Field de Intel. \u00bfEl \u00faltimo hito? Han conseguido crear un chip 3DIC con l\u00f3gica integrada y de 4 capas. Os contamos los detalles.<\/p>\n\n\n\n<p>La idea de apilar varios chips e interconectarlos en vertical 3DIC, en el mercado ya la hemos visto en forma de las memoria HBM, pero el hecho de unificar memoria y l\u00f3gica en un dise\u00f1o 3DIC o incluso varias capas de chips basados en la l\u00f3gica es mucho m\u00e1s dif\u00edcil. Mientras que en el caso de la memoria HBM hemos visto dise\u00f1os de hasta 4 chips apilados, en el caso de la l\u00f3gica+memoria o l\u00f3gica+l\u00f3gica hemos visto solo composiciones de dos chips.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Consiguen apilar hasta 4 capas de chips en un dise\u00f1o 3DIC<\/h2>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/hardzone.es\/app\/uploads-hardzone.es\/2021\/07\/4-Capas-Chip-Ime.jpg\" alt=\"4 Capas Chip\" class=\"wp-image-640641\" \/><\/figure><\/div>\n\n\n\n<p>Aunque con la memoria HBM que se encuentra en las tarjetas gr\u00e1ficas de alto rendimiento ya utiliza una configuraci\u00f3n de 4 capas, todas de memoria,<strong> el Instituto Estadounidense de Microelectronics, el IMC, ha conseguido un hito tecnol\u00f3gico que permite que hasta 4 capas de chips o semiconductores puedan ser apiladas formando un solo chip en una configuraci\u00f3n 3DIC de cuatro capas<\/strong>.<\/p>\n\n\n\n<p>El planteamiento que propone el IME se basa en combinar un par de obleas frente a frente, de tal manera que ambas se conectan por el mismo lado, al cual vamos a llamar A. Para luego conectar los otros dos chips en los extremos pero conectados la cara reversa o B. Una vez se ha hecho este procedimiento, se crean canales para que las <a href=\"https:\/\/hardzone.es\/reportajes\/que-es\/tsv-vias-silicio-chip-procesador\/\">v\u00edas a trav\u00e9s de silicio<\/a> atraviesen los cuatro chips, permitiendo as\u00ed la interconexi\u00f3n entre los cuatro chips que forman la composici\u00f3n <a href=\"https:\/\/hardzone.es\/tutoriales\/rendimiento\/3dic-intel-amd\/\">3DIC<\/a>.<\/p>\n\n\n\n<p>El problema de una pila de chips es el ahogamiento termal entre los diferentes chips, el cual se vuelve m\u00e1s complejo a medida que la pila se va haciendo m\u00e1s grande en lo que a su n\u00famero de componentes se refiere. Es por ese motivo que por ejemplo la memoria HBM 3 no ha visto a\u00fan la luz debido al debate interno sobre si aumentar la cantidad de chips a menor velocidad y con ello el ancho del bus o la velocidad del bus en s\u00ed misma. En ambos planteamientos el desaf\u00edo es el mismo, la temperatura.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">\u00bfSer\u00e1 adoptado por Intel y\/o AMD?<\/h2>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/hardzone.es\/app\/uploads-hardzone.es\/2021\/03\/CPU-interrogante-gigante.jpg\" alt=\"CPU ? Interrogante\" class=\"wp-image-577081\" \/><\/figure><\/div>\n\n\n\n<p>Pues no lo sabemos, por el momento la apuesta de Intel y AMD parece ser por sistemas 2.5DIC en los que varios chips est\u00e1n conectados en un interposer com\u00fan, algunos de ellos son chips cl\u00e1sicos y los otros son 3DIC. Por el momento tanto AMD como Intel no tienen pensado utilizar v\u00edas a trav\u00e9s de silicio, sino lo que se llama Silicon Bridges o Puentes de Silicio, al menos para conectar los diferentes componentes del MCM sobre el interposer.<\/p>\n\n\n\n<p>Otra cosa distinta es la composici\u00f3n en vertical, el hecho de a\u00f1adir hasta 4 chips permite un concepto cuanto menos interesante. El cual consistir\u00eda que al igual que el Lakefield separar el Chipset o Southbridge del resto de la CPU por un lado, por el otro se basar\u00eda en el a\u00f1adido de cach\u00e9 de \u00faltimo nivel adicional en una o las dos capas restantes. El aumento de la cach\u00e9 de \u00faltimo nivel gracias al 3DIC es crucial de cara al rendimiento en ciertas aplicaciones que requieren tanto ancho de banda como capacidad de memoria. Donde la soluci\u00f3n normalmente es utilizar complejos sistemas de memoria HBM c\u00f3mo llevar\u00e1n los futuros Sapphire Rapids de Intel.<\/p>\n\n\n\n<p><strong>Fuente:<\/strong> <a href=\"https:\/\/hardzone.es\/noticias\/procesadores\/3dic-4-capas-cpu-futuro\/\" target=\"_blank\" rel=\"noreferrer noopener\">HardZone<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>En el primer caso podemos hablar de la V-Cache que AMD ha integrado recientemente en los [&hellip;]<\/p>\n","protected":false},"author":13,"featured_media":29615,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[4],"tags":[],"class_list":["post-29614","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-noticas"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.1.1 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Logran fabricar una CPU de 4 capas, \u00bfas\u00ed ser\u00e1n los chips del futuro? -<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/\" \/>\n<meta property=\"og:locale\" content=\"es_ES\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Logran fabricar una CPU de 4 capas, \u00bfas\u00ed ser\u00e1n los chips del futuro? -\" \/>\n<meta property=\"og:description\" content=\"En el primer caso podemos hablar de la V-Cache que AMD ha integrado recientemente en los [&hellip;]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/\" \/>\n<meta property=\"article:published_time\" content=\"2021-07-21T13:57:04+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2021-07-21T13:57:07+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/goldenti.com\/site\/wp-content\/uploads\/2021\/07\/Captura-40.png\" \/>\n\t<meta property=\"og:image:width\" content=\"839\" \/>\n\t<meta property=\"og:image:height\" content=\"440\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Escrito por\" \/>\n\t<meta name=\"twitter:data1\" content=\"\" \/>\n\t<meta name=\"twitter:label2\" content=\"Tiempo de lectura\" \/>\n\t<meta name=\"twitter:data2\" content=\"4 minutos\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/\"},\"author\":{\"name\":\"\",\"@id\":\"\"},\"headline\":\"Logran fabricar una CPU de 4 capas, \u00bfas\u00ed ser\u00e1n los chips del futuro?\",\"datePublished\":\"2021-07-21T13:57:04+00:00\",\"dateModified\":\"2021-07-21T13:57:07+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/\"},\"wordCount\":648,\"image\":{\"@id\":\"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/goldenti.com\/site\/wp-content\/uploads\/2021\/07\/Captura-40.png\",\"articleSection\":[\"Noticas\"],\"inLanguage\":\"es\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/\",\"url\":\"https:\/\/goldenti.com\/site\/logran-fabricar-una-cpu-de-4-capas-asi-seran-los-chips-del-futuro\/\",\"name\":\"Logran fabricar una CPU de 4 capas, \u00bfas\u00ed ser\u00e1n los chips del futuro? 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